In the manufacture of products from hard substances such as glass, nickel, silicon and ceramics, for many uses it is necessary to provide the products with one or more high precision polished surfaces. This may be done by abrading and/or polishing one or more of the products' surfaces. An example of such products is silicon wafers sliced from monocrystalline silicon ingots.
Silicon wafers are the substrates upon which integrated circuits are built. Their surfaces must be highly polished and as free from roughness as possible. To achieve this state, after being cut from a monocrystalline ingot the wafer top surface is lapped, chemically etched and subsequently polished to the desired degree.
The polishing process, to which the present invention relates, conventionally has consisted of two stage polishing. In the first stage, stiff pads such as "Suba" polishing pads made by Rodel, Inc., are used in conjunction with an aqueous dispersion of fine particles (slurry) to remove significant silicon stock from the top surface, leaving a noticeable topography, or roughness on the wafer surface. Typically the surface at the end of the first stage of polishing will exhibit a root mean square (rms) roughness of approximately 300 Angstroms.
Conventionally, in the final stage of polishing softer finishing pads, such as "Politex" polishing pads made by Rodel, Inc., are used in conjunction with a polishing slurry to remove any residual defects from the high areas of the wafer top surface. After final polishing the wafer surface must be extremely smooth, exhibiting a reduced Root Mean Square (rms) roughness normally of less than 10 Angstroms.
Typically roughness is determined on a very fine scale, e.g. via a 2 micron by 2 micron scan area using Atomic Force Microscopy (AFM). However, significant variations in topography may exist over a much larger scale than can be measured by this technique. Such large scale roughness is generally termed "texture" Currently, no generally accepted method for measuring texture exists in the silicon industry. The most widely used qualitative tool is Nomarski microscopy. A need exists for an improved polishing technique, i.e. one that will polish a silicon wafer so that it exhibits no visible texture when viewed by Nomarski microscopy at 50.times. magnification.
The pads conventionally used in the first stage of polishing, the stock removal stage, are non-woven fabric impregnated by in-situ coagulated elastomer, such as a polyurethane. Abrasive filler may be incorporated in the fibrous pad. Budinger, et al. U.S. Pat. No.4,927,432 describes such pads. These pads are designed for rapid stock removal without consideration of the resultant wafer surface texture.
The type of pad conventionally used in the final stage of polishing is a fabric substrate coated with a cellular layer of coagulated elastomer, such as a polyurethane. The pad has a soft suede-like surface with a cellular structure that is open at the surface of the pad, enhancing the transport of the polishing slurry to the wafer surface. In this step the wafer microroughness is significantly reduced preparing the surface for subsequent integrated circuit manufacture. The production of such material to make such a pad is described in Hulsiander, et al., U.S. Pat. No. 3,284,274.
During the initial period of the second polishing step, the softness of the conventional final polishing pad causes it to conform to the surface being polished, making elimination of microroughness relatively easy. However, the softness generally results in a nearly complete inability to remove texture. Thus, a desirable second or final polishing pad would be one that can simultaneously remove texture while creating a low microroughness surface.
While silicon has been discussed, similar processes and problems are encountered with the polishing of a variety of other materials including glass, ceramics and nickel.